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Microchip Technology /ATSAMV71Q20B /RSWDT /MR

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Interpret as MR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0WDV0 (WDFIEN)WDFIEN 0 (WDRSTEN)WDRSTEN 0 (WDDIS)WDDIS 0ALLONES0 (WDDBGHLT)WDDBGHLT 0 (WDIDLEHLT)WDIDLEHLT

Description

Mode Register

Fields

WDV

Watchdog Counter Value
WDFIEN

Watchdog Fault Interrupt Enable
WDRSTEN

Watchdog Reset Enable
WDDIS

Watchdog Disable
ALLONES

Must Always Be Written with 0xFFF
WDDBGHLT

Watchdog Debug Halt
WDIDLEHLT

Watchdog Idle Halt

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data